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-- Company: 
-- Engineer:
--
-- Create Date:   17:56:35 03/03/2012
-- Design Name:   IR
-- Module Name:   C:/Users/Sebas/Desktop/proyectoAIC/processor-aic-ceu-11-12/tb_IR.vhd
-- Project Name:  Procesador
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: IR
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use IEEE.std_logic_arith.all;

ENTITY tb_IR_vhd IS
END tb_IR_vhd;

ARCHITECTURE behavior OF tb_IR_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT IR
	PORT(
		inst_word_i : IN std_logic_vector(17 downto 0);
		clk : IN std_logic;          
		ir_sel: in STD_LOGIC;
		ir_out : OUT std_logic_vector(17 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk :  std_logic := '0';
	SIGNAL inst_word_i :  std_logic_vector(17 downto 0) := (others=>'0');

	--Outputs
	SIGNAL ir_out :  std_logic_vector(17 downto 0);
	SIGNAL ir_sel: STD_LOGIC := '0';

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: IR PORT MAP(
		ir_out => ir_out,
		inst_word_i => inst_word_i,
		clk => clk,
		ir_sel => ir_sel
	);
	
	clk <= not clk after 25 ns; --periodo de 50 ns;

	tb : PROCESS
	BEGIN
					
		ir_sel <= '1';
		inst_word_i <= conv_std_logic_vector(3,18);		
		wait for 49 ns;
		
		assert (ir_out = conv_std_logic_vector(3,18))
				report "Error al leer el 3"
				severity FAILURE;

		ir_sel <= '0';
		inst_word_i <= conv_std_logic_vector(100,18);					
		
		wait for 50 ns;
		
		assert (ir_out = conv_std_logic_vector(3,18))
				report "Error al deshabilitar ir_sel"
				severity FAILURE;

		ir_sel <= '1';
		wait for 50 ns;
		
		assert (ir_out = conv_std_logic_vector(100,18))
				report "Error al re-habilitar ir_sel"
				severity FAILURE;
									
									
		 report ("**********TESTS DE IR SUPERADOS**********")
		 severity NOTE;
		wait; -- will wait forever
	END PROCESS;
	
END;
